Eecient Multiplier Architectures for Galois Fields Gf (2 4n )

This contribution introduces a new class of multipliers for nite elds GF ((2 n) 4). The architecture is based on a modiied version of the Karatsuba-Ofman algorithm (KOA). By determining optimized eld polynomials of degree four, the last stage of the KOA and the modulo reduction can be combined. This saves computation and area in VLSI implementations. The new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with KOA-based architectures with separate modulo reduction. The new multipliers lead to highly modular architectures an are thus well suited for VLSI implementations. Three types of eld polynomials are introduced and conditions for their existence are established. For the small elds where n = 2; 3; : : : ; 8, which are of primary technical interest, optimized eld polynomials were determined by an exhaustive search. For each eld order, exact space and time complexities are provided.